1. Field of Invention
This invention relates to electronic drivers and more specifically, to an improved impedance control technique for significantly reducing chip size of a metal-oxide-semiconductor (MOS) field-effect transistor, which serves as a driver for double data rate synchronous dynamic random access memory (SDRAM).
2. Description of Related Art
Stub series terminated logic (SSTL) is an electrical interface for driving transmission lines commonly used with double data rate (DDR) dynamic random access memory (DRAM) integrated circuits and memory modules. SSTL comes in three different standards as defined by the JEDEC Solid State Technology Association: SSTL—2, SSTL—3, and SSTL—18. SSTL assumes that transmission line termination is required. As such, SSTL has specifications for output impedance and different methods of termination. Impedance is a measure of opposition to current, extending the direct current (DC) concept of resistance to alternating current (AC) circuits. Termination is important for high-speed signaling because a properly terminated transmission line reduces reflections, reduces electromagnetic interference (EMI) emissions, improves settling time, and improves timing margins.
SSTL—2 and SSTL—3 are used with DDR memory and define two classes of drivers that are targeted at different termination schemes. SSTL—18 is used with DDR2 memory, which is the next generation of DDR. DDR and DDR2 are both types of SDRAM. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with a computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, which does not have a synchronized interface. DDR2 supersedes the original DDR SDRAM specification and the two are not compatible. In addition to double pumping the data bus as in DDR SDRAM (transferring data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus speed and requires lower power by running the internal clock at one quarter the speed of the data bus. The two factors combine to require a total of four (4) data transfers per internal clock cycle. Thus, without speeding up the memory cells themselves, DDR2 can effectively operate at twice the bus speed of DDR.
With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate)×2 (for bus clock multiplier)×2 (for dual rate)×64 (number of bits transferred)/8 (number of bits/byte). Thus, with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200 MB/s. Since the DDR2 clock runs at half the DDR clock rate, DDR2 memory operating at the same external data bus clock rate as DDR will provide the same bandwidth, but with higher latency, resulting in inferior performance. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.
The SSTL—18 standard has been developed particularly with the objective of providing a relatively simple upgrade path from metal oxide semiconductor (MOS) push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs. External resistors provide this isolation and also reduce the on-chip power dissipation of the drivers. Busses may be terminated by resistors to an external termination voltage. To achieve better signal integrity, the output impedance of a DDR2 driver should be controlled, i.e., calibrated to a desired impedance as established by an external resistor.
FIG. 1 illustrates a conventional output impedance control circuit 100 that compares the impedance of (or the voltage across) a driver 135 (e.g., a SSTL—18 output driver PMOS transistor and in series on-chip resistor, an output driver, a calibrated resistance driver, etc.) with the impedance of (or the voltage across) an external precision resistor 150 (e.g., a fixed resistor, a 38 ohm external precision resistor, etc.). The implementation of the conventional output impedance control circuit 100 is readily apparent to one of ordinary skill in the art. SSTL—18 requires a supply voltage to the output buffers of a DDR2 memory chip, VDDQ, to be approximately 1.8 volts, and a tracking termination voltage, VTT, to be approximately 0.9 volts (i.e., ½ of VDDQ). The driver 135 comprises “N” number of fingers 140A-N (e.g., PMOS transistor fingers, a transistor and in series on-chip resistor fingers, etc.) comprising a transistor and an in series on-chip resistor. The conventional output impedance control circuit 100 further includes a comparator 130 and a counter 120. Although the fingers 140 are illustrated as being a PMOS transistor, calibration can just as easily be performed using an NMOS transistor.
In operation, the impedance of the external precision resistor 150 is compared to the impedance of one or more of the fingers 140A-N of the driver 135. Initially, the comparator 130 compares the voltage across a first finger 140A with the voltage across the external precision resistor 150. If the voltage across the external precision resistor 150, which is input into the positive input of the comparator, is less than VTT (i.e., half of the supply voltage, typically 0.9 volts), which is the voltage into the negative input of the comparator, the output voltage of the comparator 130 is high, and the output is then fed into the counter 120. The high input of the counter 120 increments the value stored in the counter 120 by one, which enables one more finger 140B of the driver 135. The counter 120 registers the number of PMOS transistor fingers enabled in the driver 135. Enabling the finger 140B decreases the impedance of the driver 135 because the enabled fingers 140A-B are impedances connected in parallel, which reduces the equivalent impedance. The decreased impedance across the driver 135 results in a decreased voltage across it. Because the driver 135 and the external precision resistor 150 form a voltage divider, the decreased voltage across the driver 135 increases the voltage across the external precision resistor 150 towards VTT.
In one example, the supply voltage is 1.8 V, the counter 120 has four bits that enable 16 of the fingers 140, with a minimum of five of the fingers 140 enabled, where each finger 140 is set at 500 ohms, and the external precision resistor 150 is set at 38 ohms. In this example, when the counter 120 enables five of the fingers 140, the equivalent resistance is 100 ohms and the voltage across the external precision resistor 150 is 0.5 V. When ten of the fingers 140 are enabled, the equivalent resistance drops to 50 ohms and the voltage across the external precision resistor 150 increases to 0.78 V. In this example, the voltage across the external precision resistor 150 reaches half of the supply voltage when 14 of the fingers 140 are enabled, where the equivalent resistance is 36 ohms. As shown in this example, as more fingers 140 are enabled, the equivalent resistance of the fingers 140 decreases and the voltage across the external precision resistor 150 increases towards half of the supply voltage. The rate of decrease of the equivalent resistance of the fingers 140 is progressively less as more fingers are enabled (e.g., 150 ohms for five fingers, 50 ohms for 10 fingers, and 33 ohms for 15 fingers).
The resistance of each of the fingers 140 (e.g., 500 ohms in the example above) has a minimum, maximum, and typical value to allow the voltage across the external precision resistor 150 to reach half of the supply voltage. In this example, the minimum resistance is 190 ohms and the maximum resistance is 760 ohms. The typical resistance is selected far enough away from the minimum and maximum resistance values (e.g., 380 ohms), because the transistors of the driver 135 vary with process (e.g., channel length, threshold voltages, etc.), voltage (e.g., 1.7 V to 1.9 V), and temperature (e.g., −40° C. to +125° C.). If each of the fingers 140 is set to 190 ohms, 380 ohms, or 760 ohms, respectively, the voltage across the external precision resistor 150 reaches half of the supply voltage when five, ten, or 20 fingers, respectively, are enabled.
The comparator 130 compares the voltage VTT (i.e., ½ of VDDQ) in the positive input of the compactor 130, with the voltage across the external precision resistor 150 at the negative input of the comparator 130. The fingers 140A-N are interactively enabled, lowering the impedance of the driver 135 towards the impedance of the external precision resistor 150. Each time the impedance of the driver 135 is greater than the impedance of the external precision resistor 150, one more finger of the driver 135 is enabled, thereby decreasing the impedance of the driver 135. This iterative calibration process continues until the difference between the input terminals of the comparator 130 is approximately zero. At this point, the voltage drop across the external precision resistor 150 equals the voltage drop across the driver 135, both voltage drops being VTT. The current flows directly through the driver 135 and the external precision resistor 150. Accordingly, the impedance of the driver 135 matches that of the external precision resistor 150. The counter 120 stops when matching impedances of the driver 135 and external precision resistor 150 are found, such that the optimum number of enabled fingers 140A-N of the driver 135 is registered in the counter 120.
In one embodiment, the impedance of the driver 135 is approximately 38 ohms, 18 ohms from the transistor and 20 ohms from the in series on chip resistor, matching 38 ohms of the external precision resistor 150. The voltage across the driver 135 and the external precision resistor 150 are both VTT. In another embodiment, the impedance of the PMOS transistor is another value less than 21 ohms.